1. Field of the Invention
The present invention relates to erase operation or write operation to a non-volatile semiconductor memory cell, more particularly, it relates to control method and a non-volatile semiconductor memory device capable of erase operation or write operation in high speed securing reliability.
2. Description of Related Art
Japanese Laid-open Patent Publication No. 11-39887 discloses a non-volatile semiconductor memory device that intends to shorten write operation time or the like. More particularly, the non-volatile semiconductor memory device improves ISPP method that raises pulse voltage by each applied cycle with respect to write pulse waveform so as to change pulse width as well as pulse voltage.
After a write operation is started, there occurs a write pulse SP1 having a width of TPW1 and voltage of VW1 at first. In the second write operation, there occurs a write pulse SP2 having a width of TPW2 and voltage higher than VW1 by ΔV1 of step voltage.
It is also possible for the non-volatile semiconductor memory device to have structure such that a predetermined number of pulses that follow the second one have a second width and after the predetermined number of pulses, following pulses have a third width that is shorter than the second pulse. A pulse waveform of such a case is shown in FIG. 8. FIG. 8 shows that a predetermined number for the second width is two and a predetermined number for the third width is three. The second and third pulses have a second width TP200 and the fourth pulses have a third width TP300. Since the reference No. 11-39887 is an improvement of ISPP method, pulse voltage becomes higher for every applied cycle.
Japanese Laid-open Patent Publication No. 8-329694 discloses a non-volatile semiconductor memory device that intends to conduct high-speed data write operation. In the non-volatile semiconductor memory device, write operation time takes a constant time t until write voltage VPP reaches VPPmax, a maximum value of it. When write voltage VPP reaches its maximum value VPPmax by raising write voltage by ΔVPP for each write operation, data write operations after reaching VPPmax are made longer to be T(n)=4×T(n−1) keeping the predetermined value VPPmax. Since write voltage VPP is restricted, threshold voltage transition to a memory cell for next write operation is made still larger by changing write operation time.
No. 11-39887 discloses a non-volatile semiconductor memory device that intends to shorten write operation time or the like. For erase operations and write operations to a floating gate of a non-volatile semiconductor memory, tunnel current for an erase operation and hot electron current for a write operation flow depending on an electric field between a floating gate and a source or channel region that is obtained when pulse voltage is applied. An electric field generated by increased voltage from pulse voltage of a preceding cycle is added to remaining electric field, whereby level of an electric field to be applied comes to its maximum. After that, as ejection of charges from a floating gate (case of erase operation) and injection of charges to a floating gate (case of write operation) go on, an electric field becomes relaxed. Accordingly, current waveform shows transition such that tunnel current and hot electron current in their maximum levels flow when pulse voltage is applied and after reaching the maximum, the current lowers.
As shown in FIG. 8, the prior art directed to No. 11-39887 is to raise pulse voltage by each pulse and to shorten pulse width by a predetermined number of pulses while pulse voltage is made higher. While to-be-applied electric field is relaxed by tunnel current along with a predetermined declined waveform, there occurs a phenomenon that as pulse voltage becomes higher by each pulse, pulse width decreases by each pulse. That is, a new pulse waveform adds a new electric field under the situation that tunnel current or the like remains flowing in case decrease of a pulse width and to-be-applied electric field remains.
Above such situation means to add a new electric field in advance at a stage where tunnel current flows and an erase operation and the like continues. That is, this is to apply excessive electric field to a non-volatile semiconductor memory cell, which is problematic in terms of device reliability.
Needless to say, for an erase operation to a non-volatile semiconductor memory device, an electric field should be applied within a range that does not reach gate destructive voltage or the like. In the prior art directed to No. 11-39887, a to-be-applied electric field is added by each pulse. Accordingly, it is necessary to restrict a to-be-applied electric field at an initial stage of an erase operation or the like within a range of device resistibility against high voltage. Therefore, tunnel current or the like is restricted at an initial stage of an erase operation or the like. As a result, an erase operation cannot be conducted efficiently.
Furthermore, the prior art directed to No. 8-329694 is intended to achieve high-speed data write. After write voltage VPP reaches its maximum voltage VPPmax, time for write operation is taken longer so as to surely conduct each write operation.
However, each time for data-write becomes longer at latter stages that are nearly end of a write operation. In case a data-write finishes in the middle of a write period, even after the end of the data-write, unnecessary electric field is continuously applied until the write period terminates. This is problematic in terms of device reliability.